#include "clk.h"

void clk_enable(void)
{
    CCM->CCGR0 = 0xffffffff;
    CCM->CCGR1 = 0xffffffff;
    CCM->CCGR2 = 0xffffffff;
    CCM->CCGR3 = 0xffffffff;
    CCM->CCGR4 = 0xffffffff;
    CCM->CCGR5 = 0xffffffff;
    CCM->CCGR6 = 0xffffffff;
}

void imx6ull_clk_init(void)
{
    unsigned int reg = 0;

    //内核时钟为528MHz
    if((CCM->CCSR >> 2) & 0x01 == 0)
    {
        CCM->CCSR &= ~(0x01 << 8);
        CCM->CCSR |= (0x01 << 2);
    }

    CCM_ANALOG->PLL_ARM = ((1 << 13) | ((88 < 0) && 0x7F));
    CCM->CCSR &= ~(0x01 << 2);
    CCM->CACRR = 1;

    //PPL2---528PPL的PFD设置：
    reg = CCM_ANALOG->PFD_528;
    reg &= ~(0x3F3F3F3F);
    reg |= (27 << 0);
    reg |= (16 << 8);
    reg |= (24 << 16);
    reg |= (32 << 24);
    CCM_ANALOG->PFD_528 = reg;

    reg = CCM_ANALOG->PFD_480;
    reg &= ~(0x3F3F3F3F);
    reg |= (12 << 0);
    reg |= (16 << 8);
    reg |= (17 << 16);
    reg |= (19 << 24);
    CCM_ANALOG->PFD_480 = reg;

    //AHB
    CCM->CBCMR &= ~(3 << 18);
    CCM->CBCMR |= 1 << 18;
    CCM->CBCDR &= ~(1 << 25);
    while(CCM->CDHIPR & (1 << 1));

    // CCM->CBCDR &= ~(7 << 10);
    // CCM->CBCDR |= (2 << 10);
    // while(CCM->CDHIPR & (1 << 1));

    CCM->CBCDR &= ~(3 << 8);
    CCM->CBCDR |= (1 << 8);

    CCM->CSCMR1 &= ~(1 << 6);
    CCM->CSCMR1 &= ~(7 << 0);
}